// Created by 56_editfiles.t from 56_editfiles.v
// Created by 56_editfiles.t from 56_editfiles.v
// DESCRIPTION: Verilog::Preproc: Example source code
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007-2012 by Wilson Snyder.


a_front_matter;

`celldefine
// lint_checking HEADER
module a;
   wire inside_module_a;  /* // double cmt */
endmodule
`endcelldefine