module v_v2k (
   clk, rst, sig1, sig2);
   parameter WIDTH = 16;
   input clk;
   wire [1:2][3:4] netmd;
   input rst;
   input [WIDTH:0] sig1;
   output reg [WIDTH:0] sig2;
   v_v2k_sub sub (.net1(netmd[1]));
endmodule

module v_v2k_sub (
   net1);
   input [3:4] net1;
endmodule